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Tesis:

Variability-Aware Sensor Design in the Nanoscale CMOS Era

  • Autor: APARICIO CERQUEIRA, Hernán

  • Título: Variability-Aware Sensor Design in the Nanoscale CMOS Era

  • Fecha: 2021

  • Materia: Sin materia definida

  • Escuela: E.T.S. DE INGENIEROS DE TELECOMUNICACION

  • Departamentos: INGENIERIA ELECTRONICA

  • Acceso electrónico: http://oa.upm.es/67649/

  • Director/a 1º: ITUERO HERRERO, Pablo

  • Resumen: CMOS technology continues to shrink, providing benefits like higher transistor densities, lower dynamic power consumption or improved operating frequencies. However, these benefits are accompanied by undesirable side effects that make the electronic systems design process more complex. Process variations, timing uncertainties, temperature variation, power supply fluctuations, and aging are examples of the difficulties that integrated circuit designers face to develop the future CPUs and GPUs. Nowadays, technology nodes below 10 nm have become the industry standard for high-end integrated circuits, making the design incredibly challenging due to the extreme variability environment. The industry's main concerns about these variations are related to the loss of performance, reliability, and the cost of low fabrication yield. The complexity associated with each new CMOS technology node is due to the exacerbated lithographic variations that pose a significant technical challenge to process engineers. The ability to control the process directly impacts the fabrication yield of the integrated circuit. Thermal variations, caused by exceptionally high dense chips along with very localized fast-changing workloads, and extended temperature ranges for novel applications have, as well, pushed the limits of the technology. For instance, the workload current can raise from a couple of milliamps to a couple of amps in a few seconds, prone to creating stressful on-chip temperature gradients both in time and space. Power supply variations have turned into a first-level design restriction. Interconnection resistances have increased as the wires get smaller rising the IR drop in the power supply network. The transistors high-density also affects power supply as the clock frequency, or power gating create large current swings and make the supply voltage fluctuations go beyond safe operating margins. Aging variations, related to the degradation of the integrated circuits with normal use, have also gained importance with the scaling down of the technology. In this scenario of extreme variability, one of the most common solutions to improve the reliability of any chip is the idea of self-awareness, i.e., to precisely understand what is happening with the process, power supply, temperature, and aging (PVTA) variations inside the ICs. And this can be achieved through the allocation of on-chip monitoring infrastructures that are becoming more and more crucial. PVTA monitors have become fundamental for current and future designs that aim at exploiting all the technological possibilities. This thesis presents four novel sensors that address some of the acutest problems associated with PVTA variability. The first contribution approaches power supply noise in current nanometer technologies, which represents a growing risk, mainly because of the uncertainties it produces in the critical paths delays, resulting in erroneous computations. These noticeably short variations can also affect the functionality of analog circuits like a comparator or an analog digital converter (ADC). To tackle these issues and to have better power management, on-line power supply monitors have become one standard solution. Traditional approaches use an external reference and are sensitive to temperature and process variations or present high latency. The first proposed sensor is based on a novel detector circuitry that employs a feedback loop that works without an external reference and is hardened against temperature and process variations to deal with the power supply noises. The sensor was designed in the 40 nm CMOS technology node, running at 1.1 V and has been validated for a temperature range from 0 °C to 85 °C covering all process corners. Also, considering the 3