Tesis:
High-level power estimation of DSP circuits implemented in FPGAS
- Autor: JEVTIC, Ruzica
- Título: High-level power estimation of DSP circuits implemented in FPGAS
- Fecha: 2009
- Materia: Sin materia definida
- Escuela: E.T.S. DE INGENIEROS DE TELECOMUNICACION
- Departamentos: INGENIERIA ELECTRONICA
- Acceso electrónico:
- Director/a 1º: CARRERAS VAQUER, Carlos
- Resumen: Power consumption in microelectronic devices and circuits has become a critical design concern in recent years due to the rapid growth of personal wireless communications, battery-powered devices and portable digital applications. Furthermore, reliability concerns and packaging costs have made power optimization relevant not only for battery-powered applications. The largest impact on power reduction can be achieved at the system level where architecture and algorithms are to be defined. Selecting the most power efficient algorithm out of many available requires a fast and accurate way to estimate the power consumption of any implementation, so as to avoid time-consuming low-level implementations of each possible design architecture.
This work is oriented towards the high-level dynamic power estimation of DSP-oriented designs implemented in a chosen target hardware architecture. According to the different power features of logic and communication design segments, the presented power estimation methodology includes two different models. One is used for power estimation of the global routing employed for interconnections between the components and depends on their mutual distance and shape. The other is used for both, local interconnect and logic, power estimation of the components. The complete methodology in this work has been applied to DSP circuits implemented in modern Field Programmable Gate Array devices (FPGAs). High-level interconnection power estimation is a difficult task due to the extremely scarce information on global routes available at these levels of abstraction. This work proposes a power model that depends on the mutual distance of the components and their shape. There are only two input parameters to the model: the relative position of the components and the ordering of the pins on the components' boundaries. Although simple, the model takes advantage of the router properties and is capable of giving fast and highly accurate estimates for DSP-oriented designs, with the mean relative error of the interconnect power model lying within 10% of the physical measurements. High-level logic power estimation is a more studied topic in the literature. However, it often includes exhaustive low-level simulations needed for the model characterization. This work presents the methodology for high-level logic power estimation which is based on the component's structure and the analytical computation of the switching activity produced inside the component in the presence of correlated inputs. Glitching generated inside the component is also included in the model by using a novel approach for its estimation. Compared to other proposed power estimation methods, the number of circuit simulations needed for characterizing the power model of the component is highly reduced. Another important contribution is the application of the presented methodology to heterogeneous FPGA resources, so it can be used for both configurable logic-based blocks and specialized embedded blocks. Again, the mean relative error of the component power models lies within 10% of the physical measurements with a maximum error of 25%. The complete model that includes both interconnect and logic power models, has been characterized and verified by on-board power measurements, instead of using low-level estimation tools which often lack the required accuracy. Beside the accuracy, additional problems with low-level estimation tools are encountered when complex designs with many signals are to be modelled, as these tools require high amounts of memory and long execution times. As a result, it is preferred that the power estimation models are characterized by on-board measurements. The measurement system in this work is designed in order to facilitate the separation of the static power, the clock power, the power of the global interconnects and the power consumed in the logic. Consequently, it has been used for the verification of both models separately and also when they were used together in order to estimate the total dynamic power consumption of the DSP circuits. Finally, the complete model performance has been explored over a wide range of input parameters, signal components and design positions on a chip. The accuracy of the model has also been verified for some DSP benchmarks. The results suggest that the proposed model is suitable for integration with high-level power optimization techniques, where accurate estimates are needed in the shortest possible time.